State of the art integrated circuits should be capable of rejecting high frequency noise in the input digital signals. For this reason, the prior art has shown the use of large RC time constant filters in the input circuitry of the integrated circuits. The large RC time constant delays the applicaton of the applied input signal to subsequent circuitry until the noise signal fades away, thus insulating the subsequent circuitry from the deleterious effects of the noise signal. A longer, true digital data signal gets through, while the noise signal does not. To effect this on-chip filtration, on-chip RC (resistor/capacitor) filters require a very large time constant (40 microseconds or larger). Conventional techniques for realizing on-chip RC filters require very large capacitance and very long transistors which not only increase the silicon chip area, but more importantly make the circuit more vulnerable to failure due to large leakage currents associated with these long devices. The conventional methods also suffer from the problem of `pulse shrinkage`.
To overcome these problems, the technique of the present invention as illustrated below can be used, which increases the effective resistance of on-chip transistors and the time constants of RC filters substantially without increasing the silicon area and also improves the pulse shrinkage problem. According to the present invention, by the use of a single long transistor on the integrated circuit chip, together with a transistor operated as a capacitor in conjunction with a comparator circuit and accompanying feedback and monitoring elements, a very large resistance in the RC time constant can be realized with a reasonable size for the transistor.